It is known to provide cache memories between respective processors of a multiprocessor system and a shared background memory. The cache memories store copies of data associated with selected addresses in the background memory. A major concern in such a system is the maintenance of consistency between the copies. When one processor updates data for a background memory address in its cache memory or in the background memory, copies of the data for that address in other cache memories may be inconsistent with the updated data.
It is known to enforce consistency by means of a cache coherence circuit. The cache coherence circuit communicates at least the background memory addresses of updated data among the cache memories. The cache memories are provided with controllers that use this information to invalidate or update inconsistent data. Thus, if a processor subsequently addresses this data, it will have to be loaded from the background memory in the case of invalidation, or it will load updated data in the case of updates. As a result, program execution in each processor can proceed using background memory addresses of shared data, without concern for inconsistency.
However, cache coherence circuits tend to be very complex, giving rise to considerable circuit overhead and/or processing delays and even design errors.